The NanoIC pilot line is a groundbreaking initiative with a bold vision: to become the world's leading R&D pilot line for semiconductor technology beyond the 2nm threshold. This project is a key component of the European Chips Act, an ambitious plan to solidify Europe's position as a global leader in the semiconductor ecosystem. By focusing on critical markets such as computing, communication, mobility, energy, and healthcare, the NanoIC pilot line aims to bridge the gap between cutting-edge research and commercial applications, driving innovation and competitiveness on a global scale.
But here's where it gets controversial... The NanoIC pilot line is not just about research; it's about turning those research insights into tangible, commercial products. To achieve this, a robust lab-to-fab conduit is essential. The NanoIC pilot line fosters innovation in computing system architectures by maturing specific semiconductor technologies, with the ultimate goal of enabling European companies to lead the way in semiconductor innovation.
Specifically, the NanoIC pilot line provides a beyond 2nm system-on-chip (SoC) pilot line, focusing on the development and maturation of advanced logic, memory, and interconnect technologies. This project is a collaborative effort, with participants engaging in ways that suit their specific needs and innovation goals. By doing so, Europe can maintain its competitiveness across the entire semiconductor value chain, from materials to systems.
The NanoIC pilot line project consortium is led by imec, with key partners including CEA-Leti (France), Fraunhofer-Gesellschaft (Germany), VTT Technical Research Center (Finland), Tyndall National Institute (Ireland), and the Center for Surface Science and Nanotechnology of the University Politehnica of Bucharest (Romania). This diverse group of experts is supported by the Flemish Government, other participating states, and the Chips Joint Undertaking, all working together to make this pilot line a success.
When it comes to the future of compute systems, the NanoIC pilot line is focused on nanosheet logic devices, which are expected to drive scaling and performance improvements for at least three more generations. Additionally, complementary field effect transistor (CFET) architectures are projected to be introduced around 2031, representing a significant shift in CMOS device design. This progression requires extensive research into new materials, process modules, equipment, and advanced patterning capabilities, with high numerical aperture extreme ultraviolet (high NA EUV) lithography playing a crucial role.
Memory innovations are also a key focus, with an emphasis on novel magnetic memories like spin orbit torque-magnetic random access memory (SOT-MRAM) and embedded Dynamic Random Access Memory (eDRAM). For eDRAM, an alternative 2T0C configuration is being developed, exploring wide bandgap semiconductors such as indium-gallium-zinc-oxide and 2D transition metal dichalcogenides. Developing a 3D memory platform to explore future memory options is also essential to address memory capacity and bandwidth challenges posed by new workloads.
To integrate different dies into systems, advanced electrical and optical interconnects are required, pushing the boundaries beyond 2nm. To further advance electrical interconnects, 3D heterogeneous integration techniques like die-to-wafer (D2W) hybrid bonding will be utilized. The NanoIC pilot line aims to target lines under 2µm, offering fine-pitch redistribution layer (FP RDL) technology based on copper lines and vias, embedded in polymers, to electrically connect dies side-by-side and enable 2.5D chiplet integration on a low-cost interposer platform.
These leading-edge logic, memory, and interconnect technologies, defined at industry-relevant dimensions, are at the core of the NanoIC pilot line. Enabling these technologies requires evaluating new processes and materials, tighter process control, and a versatile set of validation routes. Setting up relevant process modules demands investment in new processing and metrology tools, with these modules serving as the building blocks for baseline flows, continuously improving and pushing towards higher TRL.
To lower the barriers to advanced chip designs, the NanoIC pilot line provides European designers with advanced process design kits (PDKs). These comprehensive toolsets offer predictive models, cell libraries, and system-level integration resources, enabling accurate simulation and validation of integrated circuits for advanced technology nodes. By providing early access to these PDKs, circuit designers can explore upcoming chip architectures, tackle complex design challenges, and drive innovation in beyond 2nm nodes.
The NanoIC pilot line offers two complementary PDKs: pathfinding PDKs for early design exploration in cutting-edge IC technologies, and system exploration PDKs for hardware prototyping and system-level innovation. These PDKs are released throughout the project, with multiple versions of the N2 pathfinding PDK, including A14 and A7 logic PDKs. Memory PDKs are based on progress in eDRAM and SOT-MRAM, while advanced interconnect solutions can be explored through RDL, silicon interposers, and D2W hybrid bonding.
The NanoIC pilot line provides flexible access to advanced logic, memory, and interconnect technologies for the entire semiconductor ecosystem. Companies, research institutes, start-ups, and universities can collaborate to meet their innovation needs. Integrated device manufacturers and foundries can leverage the baselines to explore new modules and performance enhancements. Equipment and materials suppliers, both European and global, are invited to collaborate to test and refine new tools and processes. Start-ups, universities, and design companies have access to pathfinding PDKs for early design exploration and system exploration PDKs for hardware prototyping and system-level innovation.
Furthermore, the NanoIC pilot line is committed to nurturing the next generation of semiconductor experts. Partnering with EU Competence Centers, they offer classroom and virtual courses on beyond 2nm technologies, covering everything from semiconductor materials to SoC design. Through hands-on internships and learning programs, students gain real-world experience, while industry-oriented trainings prepare Bachelor's, Master's, and PhD students for future challenges. With expert courses, technical training, and immersive bootcamps, the NanoIC pilot line is building a skilled workforce to propel the European semiconductor industry forward.
In summary, the NanoIC pilot line is strategically positioned to bridge the gap between research and commercial applications, driving innovation and competitiveness in the semiconductor industry. This project underscores Europe's commitment to innovation, sustainability, and growth in a digital world. By advancing technologies and fostering collaboration, the NanoIC pilot line aims to consolidate Europe's leadership in the global semiconductor market.
Disclaimer: The acquisition and operation of the NanoIC pilot line are jointly funded by the Chips Joint Undertaking, the European Union's Digital Europe and Horizon Europe programs, and the participating states of Belgium (Flanders), France, Germany, Finland, Ireland, and Romania. For more information, visit nanoic-project.eu.
This article is based on a comment published in Nature Reviews Electrical Engineering (Volume 1 | December 2024 | 764–765 | 764) and will also appear in the 24th edition of our quarterly publication.
